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Cache coherency
Results: 118

#	Item
41	The NUMAchine Multiprocessor Z. Vranesic, S. Brown, M. Stumm, S. Caranci, A. Grbic, R. Grindley, M. Gusat, O. Krieger, G. Lemieux, K. Loveless, N. Manjikian Z. Zilic, T. Abdelrahman, B. Gamsa, P. Pereira, K. Sevcik, A. E Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:55 Computer hardware Computer architecture Parallel computing CPU cache Cache Central processing unit Non-Uniform Memory Access Cell Memory hierarchy Computing Cache coherency Computer memory
42	MIPS R4000 Caches and Coherency Paul Ries 1 Add to Reading List Source URL: www.hotchips.org Language: English Cache Computer memory R4000 CPU cache Computing Cache coherency Computer hardware
43	HIERARCHICAL DIRECTORY CONTROLLERS IN THE NUMACHINE MULTIPROCESSOR by Alexander Grbic Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:44 Cache coherency CPU cache Cache Dynamic random-access memory Memory hierarchy Controller Bus sniffing Scalable Coherent Interface Computing Computer hardware Computer memory
44	[removed]DESIGN-SAMZA[removed]md Shared state design (SAMZA-402) Introduction Add to Reading List Source URL: issues.apache.org Language: English Concurrent computing Cache Apache Hadoop Stream processing CPU cache Computing Cache coherency Software
45	Design and Implementation of the NUMAchine Multiprocessor A. Grbic, S. Brown, S. Caranci, R. Grindley, M. Gusat, G. Lemieux, K. Loveless, N. Manjikian , S. Srbljic , M. Stumm, Z. Vranesic and Z. Zilic Add to Reading List Source URL: www.eecg.toronto.edu Language: English - Date: 1999-09-21 22:20:54 Parallel computing Cache coherency Computer buses CPU cache Central processing unit Non-Uniform Memory Access Cache coherence Cache Conventional PCI Computing Computer hardware Computer memory
46	Microsoft PowerPoint - micro-dec-07 [Compatibility Mode] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2010-12-23 23:42:35 Application software Graphics file formats Cache QuickTime Tagged Image File Format Computing Software Cache coherency
47	Design Trade-Offs in High-Throughput Coherence Controllers Anthony-Trung Nguyen Microprocessor Research Labs Intel Corporation Santa Clara, CA[removed]removed] Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2003-09-30 19:13:24 CPU cache Cache MESI protocol Parallel computing Computing Cache coherency Computer hardware
48	Removing Architectural Bottlenecks to the Scalability of Speculative Parallelization ´ Garzar´an, Lawrence Rauchwergery , and Josep Torrellas Milos Prvulovic, Mar´ıa Jesus University of Illinois at Urbana-Champaign Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2005-03-23 12:50:54 Computer memory Cache coherency Central processing unit CPU cache Cache Multi-core processor Speedup Automatic parallelization Memory hierarchy Computing Parallel computing Computer architecture
49	OmniOrder: Directory-Based Conflict Serialization of Transactions ∗ Xuehai Qian † University of California, Berkeley Benjamin Sahelices Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2014-04-19 12:44:14 Computer hardware Computer memory CPU cache MESI protocol MSI protocol Cache Transactional memory Parallel computing Cache coherency Computing Concurrent computing
50	BulkCommit: Scalable and Fast Commit of Atomic Blocks ∗ in a Lazy Multiprocessor Environment † Xuehai Qian , Josep Torrellas Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2013-10-25 19:56:50 Computer file formats Graphics file formats Cache coherency Chunk CPU cache MESI protocol ANIM Parallel computing C dynamic memory allocation Computing Computer memory Computer hardware